There is a tendency to think of “CMOS Scaling” as an unbroken 45-year progression of systematic and orderly dimensional scaling. However, the real story is much more complex. The words “CMOS scaling” were not even used in the context of orderly dimensional scaling until the late 1990s (prior to that NMOS-only circuits dominated the industry). Our understanding of the key challenges of CMOS scaling has also changed over time. Some challenges (such as lithography) were initially perceived as significant limitations to scaling, and have become less important over time. Others (such as quantum mechanical tunneling through the gate) were initially perceived as being unimportant, but have become increasingly important over time. Of course, some challenges (such as short channel control) were recognized as critical from the beginning and have remained so. The purpose of this talk is to describe the elements of CMOS scaling – both in their historical context and as they are perceived today. Additionally, the talk will extend to “Beyond CMOS” devices and highlight where new transformational advancements are occurring or may occur in the future.